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1. general description the lpc1315/16/17/45/46/47 are arm cort ex-m3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. the arm cortex-m3 is a next generation core that offe rs system enhancements such as enhanced debug features and a higher level of support block integration. the lpc1315/16/17/45/46/47 operate at cpu frequencies of up to 72 mhz. the arm cortex-m3 cpu incorporates a 3-stage pipe line and uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. the arm cortex-m3 cpu also includes an internal prefetch unit that supports speculative branching. equipped with a highly flexible and configurable full-speed usb 2.0 device controller available on the lpc1345/46/47, this series brings unpa ralleled design flexibility and seamless integration to today?s demanding connectivity solutions. the peripheral complement of the lpc1315/16/ 17/45/46/47 includes up to 64 kb of flash memory, 8 kb or 10 kb of sram data memory, one fast-mode plus i 2 c-bus interface, one rs-485/eia-485 usart with support for synchr onous mode and smart card interface, two ssp interfaces, four general purpose coun ter/timers, an 8-channel, 12-bit adc, and up to 51 general purpose i/o pins. 2. features and benefits ? system: ? arm cortex-m3 r2p1 processor, runnin g at frequencies of up to 72 mhz. ? arm cortex-m3 built-in nested vectored interrupt controller (nvic). ? non maskable interrupt (nmi) input se lectable from seve ral input sources. ? system tick timer. ? memory: ? up to 64 kb on-chip flash program memory with a 256 byte page erase function. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. flash updates via usb supported. ? up to 4 kb on-chip eeprom data memory with on-chip api support. ? up to 12 kb sram data memory. ? 16 kb boot rom with api support for usb api, power control, eeprom, and flash iap/isp. lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller; up to 64 kb fl ash; up to 12 kb sram; usb device; usart; eeprom rev. 3 ? 20 september 2012 product data sheet
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 2 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller ? debug options: ? standard jtag test interface for bsdl. ? serial wire debug. ? support for etm arm cortex-m3 debug time stamping. ? digital peripherals: ? up to 51 general purpose i/o (gpio) pi ns with configurable pull-up/pull-down resistors, repeater mode, input inverter, and pseudo open-drain mode. eight pins support programmable glitch filter. ? up to 8 gpio pins can be selected as edge and level sensitive interrupt sources. ? two gpio grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of gpio pins. ? high-current source output driver (20 ma) on one pin (p0_7). ? high-current sink driver (20 ma) on true open-drain pins (p0_4 and p0_5). ? four general purpose counter/timers with a total of up to 8 capture inputs and 13 match outputs. ? programmable windowed watchdog timer (wwdt) with a internal low-power watchdog oscillator (wdo). ? repetitive interrup t timer (ri timer). ? analog peripherals: ? 12-bit adc with eight input channels and sa mpling rates of up to 500 ksamples/s. ? serial interfaces: ? usb 2.0 full-speed device controller (lpc1345/46/47) with on-chip rom-based usb driver library. ? usart with fractional baud rate generati on, internal fifo, a full modem control handshake interface, and support for rs-485/9-bit mode and synchronous mode. usart supports an asynchronous smart card interface (iso 7816-3). ? two ssp controllers with fifo an d multi-protocol capabilities. ? i 2 c-bus interface supporting the full i 2 c-bus specification and fast-mode plus with a data rate of up to 1 mb it/s with multiple address recognition and monitor mode. ? clock generation: ? crystal oscillator with an op erating range of 1 mhz to 25 mhz (system oscillator) with failure detector. ? 12 mhz high-frequency internal rc oscilla tor (irc) trimmed to 1 % accuracy over the entire voltage and temperature range. the irc can optionally be used as a system clock. ? internal low-power, low-frequency watchdog oscillator (wdo) with programmable frequency output. ? pll allows cpu operation up to the maxi mum cpu rate with the system oscillator or the irc as clock sources. ? a second, dedicated pll is provided for usb (lpc1345/46/47). ? clock output function with divi der that can reflec t the crystal oscillator, the main clock, the irc, or the watchdog oscillator. ? power control: ? four reduced power modes: sleep, deep-sleep, power-down, and deep power-down. ? power profiles residing in boot rom allow optimized performance and minimized power consumption for any given application through one simple function call.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 3 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller ? processor wake-up from deep-sleep and power-down modes via reset, selectable gpio pins, watchdog interrupt, or usb port activity. ? processor wake-up from deep power-down mode using one special function pin. ? integrated pmu (power management unit) to minimize power consumption during sleep, deep-sleep, power-down, and deep power-down modes. ? power-on reset (por). ? brownout detect with up to four separate thresholds for interrupt and forced reset. ? unique device serial number for identification. ? single 3.3 v power supply (2.0 v to 3.6 v). ? temperature range ? 40 ? c to +85 ? c. ? available as LQFP64, lqfp 48, and hvqfn33 package. 3. applications 4. ordering information ? consumer peripherals ? handheld scanners ? medical ? usb audio devices ? industrial control table 1. ordering information type number package name description version lpc1345fhn33 hvqfn33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1345fbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1346fhn33 hvqfn33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1346fbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1347fhn33 hvqfn33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1347fbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1347fbd64 LQFP64 LQFP64: plastic low pr ofile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc1315fhn33 hvqfn33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1315fbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1316fhn33 hvqfn33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1316fbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1317fhn33 hvqfn33 plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 ? 7 ? 0.85 mm n/a lpc1317fbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 ? 7 ? 1.4 mm sot313-2 lpc1317fbd64 LQFP64 LQFP64: plastic low pr ofile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 4 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 4.1 ordering options table 2. ordering options type number flash [kb] sram [kb] eeprom [kb] usb device ssp i2c/ fm+ adc channels gpio pins sram0 usb sram sram1 lpc1345fhn33 32 8 2 - 2 yes 2 1 8 26 lpc1345fbd48 32 8 2 - 2 yes 2 1 8 40 lpc1346fhn33 48 8 2 - 4 yes 2 1 8 26 lpc1346fbd48 48 8 2 - 4 yes 2 1 8 40 lpc1347fhn33 64 8 2 2 4 yes 2 1 8 26 lpc1347fbd48 64 8 2 2 4 yes 2 1 8 40 lpc1347fbd64 64 8 2 2 4 yes 2 1 8 51 lpc1315fhn33 32 8 - - 2 no 2 1 8 28 lpc1315fbd48 32 8 - - 2 no 2 1 8 40 lpc1316fhn33 48 8 - - 4 no 2 1 8 28 lpc1316fbd48 48 8 - - 4 no 2 1 8 40 lpc1317fhn33 64 8 - 2 4 no 2 1 8 28 lpc1317fbd48 64 8 - 2 4 no 2 1 8 40 lpc1317fbd64 64 8 - 2 4 no 2 1 8 51
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 5 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 5. block diagram (1) available on lqfp48 and LQFP64 packages only. (2) ct16b0_cap1, ct16b1_cap1, ct32b1_cap1 inputs available on LQFP64 packages only. ct32 b0_cap0 input available on lqfp48 and LQFP64 packages only. fig 1. block diagram sram 8/10/12 kb arm cortex-m3 test/debug interface high-speed gpio ahb to apb bridge clock generation, power control, system functions reset swd, jtag lpc1315/16/17 lpc1345/46/47 slave slave flash 32/48/64 kb eeprom 2/4 kb slave slave rom 16 kb slave ahb-lite bus gpio ports 0/1 clkout irc, wdo system oscillator por pll0 usb pll bod 12-bit adc usart/ smartcard interface ad[7:0] rxd txd cts, rts, dtr sclk gpio pin interrupt 32-bit counter/timer 0 ct32b0_mat[3:0] ct32b0_cap[1:0] (2) 32-bit counter/timer 1 ct32b1_mat[3:0] ct32b1_cap[1:0] (2) dcd , dsr (1) , ri (1) 16-bit counter/timer 1 windowed watchdog timer gpio group0 interrupt ct16b1_mat[1:0] 16-bit counter/timer 0 ct16b0_mat[2:0] ct16b0_cap[1:0] (2) ct16b1_cap[1:0] (2) gpio pins gpio pins gpio group1 interrupt gpio pins system bus ssp0 sck0, ssel0, miso0, mosi0 ssp1 sck1, ssel1, miso1, mosi1 i 2 c-bus iocon system control pmu ri timer scl, sda xtalin xtalout usb device controller (lpc1345/46/47) usb_dp usb_dm usb_vbus usb_ftoggle, usb_connect 002aag241 master slave
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 6 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 6. pinning information 6.1 pinning fig 2. pin configuration hvqfn33 package (lpc1315/16/17 - no usb) 002aag870 transparent top view pio0_8/miso0/ct16b0_mat0 pio0_20/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1/swo v dd swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio0_22/ad6/ct16b1_mat1/miso1 xtalin tdi/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2 tms/pio0_12/ad1/ct32b1_cap0 reset/pio0_0 tdo/pio0_13/ad2/ct32b1_mat0 pio1_19/dtr/ssel1 trst/pio0_14/ad3/ct32b1_mat1 pio0_3 pio0_4/scl pio0_5/sda pio0_21/ct16b1_mat0/mosi1 pio1_23/ct16b1_mat1/ssel1 pio1_24/ct32b0_mat0 pio0_6/r/sck0 pio0_7/cts pio0_19/txd/ct32b0_mat1 pio0_18/rxd/ct32b0_mat0 pio0_17/rts/ct32b0_cap0/sclk v dd pio1_15/dcd/ct16b0_mat2/sck1 pio0_23/ad7 pio0_16/ad5/ct32b1_mat3/wakeup swdio/pio0_15/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss lpc1315fhn33 lpc1316fhn33 lpc1317fhn33
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 7 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 3. pin configuration hvqfn33 package (lpc1345/46/47 - with usb) 002aag874 transparent top view pio0_8/miso0/ct16b0_mat0 pio0_20/ct16b1_cap0 pio0_2/ssel0/ct16b0_cap0 pio0_9/mosi0/ct16b0_mat1/swo v dd swclk/pio0_10/sck0/ct16b0_mat2 xtalout pio0_22/ad6/ct16b1_mat1/miso1 xtalin tdi/pio0_11/ad0/ct32b0_mat3 pio0_1/clkout/ct32b0_mat2/usb_ftoggle tms/pio0_12/ad1/ct32b1_cap0 reset/pio0_0 tdo/pio0_13/ad2/ct32b1_mat0 pio1_19/dtr/ssel1 trst/pio0_14/ad3/ct32b1_mat1 pio0_3/usb_vbus pio0_4/scl pio0_5/sda pio0_21/ct16b1_mat0/mosi1 usb_dm usb_dp pio0_6/usb_connect/sck0 pio0_7/cts pio0_19/txd/ct32b0_mat1 pio0_18/rxd/ct32b0_mat0 pio0_17/rts/ct32b0_cap0/sclk v dd pio1_15/dcd/ct16b0_mat2/sck1 pio0_23/ad7 pio0_16/ad5/ct32b1_mat3/wakeup swdio/pio0_15/ad4/ct32b1_mat2 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area 33 v ss lpc1345fhn33 lpc1346fhn33 lpc1347fhn33
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 8 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 4. pin configuration lqfp48 package (lpc1315/16/17 - no usb) lpc1315fbd48 lpc1316fbd48 lpc1317fbd48 pio1_25/ct32b0_mat1 pio1_13/dtr/ct16b0_mat0/txd pio1_19/dtr/ssel1 trst/pio0_14/ad3/ct32b1_mat1 reset/pio0_0 tdo/pio0_13/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2 tms/pio0_12/ad1/ct32b1_cap0 v ss tdi/pio0_11/ad0/ct32b0_mat3 xtalin pio1_29/sck0/ct32b0_cap1 xtalout pio0_22/ad6/ct16b1_mat1/miso1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio0_20/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1/swo pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio1_26/ct32b0_mat2/rxd pio1_21/dcd/miso1 pio1_27/ct32b0_mat3/txd pio1_31 pio1_20/dsr/sck1 pio1_16/ri/ct16b0_cap0 pio0_3 pio0_19/txd/ct32b0_mat1 pio0_4/scl pio0_18/rxd/ct32b0_mat0 pio0_5/sda pio0_17/rts/ct32b0_cap0/sclk pio0_21/ct16b1_mat0/mosi1 v dd pio1_23/ct16b1_mat1/ssel1 pio1_15/dcd/ct16b0_mat2/sck1 n.c. pio0_23/ad7 n.c. v ss pio1_24/ct32b0_mat0 pio0_16/ad5/ct32b1_mat3/wakeup pio0_6/r/sck0 swdio/pio0_15/ad4/ct32b1_mat2 pio0_7/cts pio1_28/ct32b0_cap0/sclk pio1_22/ri/mosi1 pio1_14/dsr/ct16b0_mat1/rxd 002aag875 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 9 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 5. pin configuration lqfp48 package (lpc1345/46/47 - with usb) lpc1345fbd48 lpc1346fbd48 lpc1347fbd48 pio1_25/ct32b0_mat1 pio1_13/dtr/ct16b0_mat0/txd pio1_19/dtr/ssel1 trst/pio0_14/ad3/ct32b1_mat1 reset/pio0_0 tdo/pio0_13/ad2/ct32b1_mat0 pio0_1/clkout/ct32b0_mat2/usb_ftoggle tms/pio0_12/ad1/ct32b1_cap0 v ss tdi/pio0_11/ad0/ct32b0_mat3 xtalin pio1_29/sck0/ct32b0_cap1 xtalout pio0_22/ad6/ct16b1_mat1/miso1 v dd swclk/pio0_10/sck0/ct16b0_mat2 pio0_20/ct16b1_cap0 pio0_9/mosi0/ct16b0_mat1/swo pio0_2/ssel0/ct16b0_cap0 pio0_8/miso0/ct16b0_mat0 pio1_26/ct32b0_mat2/rxd pio1_21/dcd/miso1 pio1_27/ct32b0_mat3/txd pio1_31 pio1_20/dsr/sck1 pio1_16/ri/ct16b0_cap0 pio0_3/usb_vbus pio0_19/txd/ct32b0_mat1 pio0_4/scl pio0_18/rxd/ct32b0_mat0 pio0_5/sda pio0_17/rts/ct32b0_cap0/sclk pio0_21/ct16b1_mat0/mosi1 v dd pio1_23/ct16b1_mat1/ssel1 pio1_15/dcd/ct16b0_mat2/sck1 usb_dm pio0_23/ad7 usb_dp v ss pio1_24/ct32b0_mat0 pio0_16/ad5/ct32b1_mat3/wakeup pio0_6/usb_connect/sck0 swdio/pio0_15/ad4/ct32b1_mat2 pio0_7/cts pio1_28/ct32b0_cap0/sclk pio1_22/ri/mosi1 pio1_14/dsr/ct16b0_mat1/rxd 002aag876 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 10 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller see table 3 for the full pin name. fig 6. pin configuration LQFP64 package (lpc1315/16/17 - no usb) lpc1315/16/17 pio1_0 vrefn pio1_25 pio1_13 pio1_19 trst/pio0_14 reset/pio0_0 tdo/pio0_13 pio0_1 tms/pio0_12 pio1_7 pio1_11 v ss tdi/pio0_11 xtalin pio1_29 xtalout pio0_22 v dd pio1_8 pio0_20 swclk/pio0_10 pio1_10 pio0_9 pio0_2 pio0_8 pio1_26 pio1_21 pio1_27 pio1_2 pio1_4 v dd pio1_1 vrefp pio1_20 pio1_16 pio0_3 pio0_19 pio0_4 pio0_18 pio0_5 pio0_17 pio0_21 v dda pio1_17 v dd pio1_23 pio1_15 n.c. pio0_23 n.c. v ssa pio1_24 v ss pio1_18 pio0_16 pio0_6 swdio/pio0_15 pio0_7 pio1_22 pio1_28 pio1_3 pio1_5 pio1_14 002aag581 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 11 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 7. pin configuration LQFP64 package (lpc1345/46/47 - with usb) lpc1345/46/47 pio1_0 vrefn pio1_25 pio1_13 pio1_19 trst/pio0_14 reset/pio0_0 tdo/pio0_13 pio0_1 tms/pio0_12 pio1_7 pio1_11 v ss tdi/pio0_11 xtalin pio1_29 xtalout pio0_22 v dd pio1_8 pio0_20 swclk/pio0_10 pio1_10 pio0_9 pio0_2 pio0_8 pio1_26 pio1_21 pio1_27 pio1_2 pio1_4 v dd pio1_1 vrefp pio1_20 pio1_16 pio0_3 pio0_19 pio0_4 pio0_18 pio0_5 pio0_17 pio0_21 v dda pio1_17 v dd pio1_23 pio1_15 usb_dm pio0_23 usb_dp v ssa pio1_24 v ss pio1_18 pio0_16 pio0_6 swdio/pio0_15 pio0_7 pio1_22 pio1_28 pio1_3 pio1_5 pio1_14 002aag561 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 12 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 6.2 pin description table 3. pin description (lpc1315/16/17 - no usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description reset /pio0_0 4 3 2 [2] i; pu i reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. this pin also serves as the debug select input. low level selects the jtag boundary scan. high level selects the arm swd debug mode. -i/o pio0_0 ? general purpose digital input/output pin. pio0_1/clkout/ ct32b0_mat2 543 [3] i; pu i/o pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. -o clkout ? clockout pin. -o ct32b0_mat2 ? match output 2 for 32-bit timer 0. pio0_2/ssel0/ ct16b0_cap0 13 10 8 [3] i; pu i/o pio0_2 ? general purpose digital input/output pin. i/o ssel0 ? slave select for ssp0. i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3 19 14 9 [3] i; pu i/o pio0_3 ? general purpose digital input/output pin. pio0_4/scl 20 15 10 [4] ia i/o pio0_4 ? general purpose digital input/output pin (open-drain). -i/o scl ? i 2 c-bus clock input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 21 16 11 [4] ia i/o pio0_5 ? general purpose digital input/output pin (open-drain). -i/o sda ? i 2 c-bus data input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/r/ sck0 29 22 15 [3] i; pu i/o pio0_6 ? general purpose digital input/output pin. --r ? reserved. -i/o sck0 ? serial clock for ssp0. pio0_7/cts 30 23 16 [5] i; pu i/o pio0_7 ? general purpose digital input/output pin (high-current output driver). -i cts ? clear to send input for usart. pio0_8/miso0/ ct16b0_mat0 36 27 17 [3] i; pu i/o pio0_8 ? general purpose digital input/output pin. -i/o miso0 ? master in slave out for ssp0. -o ct16b0_mat0 ? match output 0 for 16-bit timer 0. pio0_9/mosi0/ ct16b0_mat1/ swo 37 28 18 [3] i; pu i/o pio0_9 ? general purpose digital input/output pin. -i/o mosi0 ? master out slave in for ssp0. -o ct16b0_mat1 ? match output 1 for 16-bit timer 0. -o swo ? serial wire trace output.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 13 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller swclk/pio0_10/sck0/ ct16b0_mat2 38 29 19 [3] i; pu i swclk ? serial wire clock and test clock tck for jtag interface. -i/o pio0_10 ? general purpose digital input/output pin. -o sck0 ? serial clock for ssp0. -o ct16b0_mat2 ? match output 2 for 16-bit timer 0. tdi/pio0_11/ad0/ ct32b0_mat3 42 32 21 [6] i; pu i tdi ? test data in for jtag interface. -i/o pio0_11 ? general purpose digital input/output pin. -i ad0 ? a/d converter, input 0. -o ct32b0_mat3 ? match output 3 for 32-bit timer 0. tms/pio0_12/ad1/ ct32b1_cap0 44 33 22 [6] i; pu i tms ? test mode select for jtag interface. -i/o pio_12 ? general purpose digital input/output pin. -i ad1 ? a/d converter, input 1. -i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. tdo/pio0_13/ad2/ ct32b1_mat0 45 34 23 [6] i; pu o tdo ? test data out for jtag interface. -i/o pio0_13 ? general purpose digital input/output pin. -i ad2 ? a/d converter, input 2. -o ct32b1_mat0 ? match output 0 for 32-bit timer 1. trst /pio0_14/ad3/ ct32b1_mat1 46 35 24 [6] i; pu i trst ? test reset for jtag interface. -i/o pio0_14 ? general purpose digital input/output pin. -i ad3 ? a/d converter, input 3. -o ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio0_15/ad4/ ct32b1_mat2 52 39 25 [6] i; pu i/o swdio ? serial wire debug input/output. -i/o pio0_15 ? general purpose digital input/output pin. -i ad4 ? a/d converter, input 4. -o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio0_16/ad5/ ct32b1_mat3/wakeup 53 40 26 [7] i; pu i/o pio0_16 ? general purpose digital input/output pin. -i ad5 ? a/d converter, input 5. -o ct32b1_mat3 ? match output 3 for 32-bit timer 1. -i wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. pio0_17/rts / ct32b0_cap0/sclk 60 45 30 [3] i; pu i/o pio0_17 ? general purpose digital input/output pin. -o rts ? request to send output for usart. -i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. -i/o sclk ? serial clock input/output for usart in synchronous mode. table 3. pin description (lpc1315/16/17 - no usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 14 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller pio0_18/rxd/ ct32b0_mat0 61 46 31 [3] i; pu i/o pio0_18 ? general purpose digital input/output pin. -i rxd ? receiver input for usart. used in uart isp mode. -o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio0_19/txd/ ct32b0_mat1 62 47 32 [3] i; pu i/o pio0_19 ? general purpose digital input/output pin. -o txd ? transmitter output for usart. used in uart isp mode. -o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio0_20/ct16b1_cap0 11 9 7 [3] i; pu i/o pio0_20 ? general purpose digital input/output pin. -i ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio0_21/ct16b1_mat0/ mosi1 22 17 12 [3] i; pu i/o pio0_21 ? general purpose digital input/output pin. -o ct16b1_mat0 ? match output 0 for 16-bit timer 1. -i/o mosi1 ? master out slave in for ssp1. pio0_22/ad6/ ct16b1_mat1/miso1 40 30 20 [6] i; pu i/o pio0_22 ? general purpose digital input/output pin. -i ad6 ? a/d converter, input 6. -o ct16b1_mat1 ? match output 1 for 16-bit timer 1. -i/o miso1 ? master in slave out for ssp1. pio0_23/ad7 56 42 27 [6] i; pu i/o pio0_23 ? general purpose digital input/output pin. -i ad7 ? a/d converter, input 7. pio1_0/ct32b1_mat0 1 - - [3] i; pu i/o pio1_0 ? general purpose digital input/output pin. -o ct32b1_mat0 ? match output 0 for 32-bit timer 1. pio1_1/ct32b1_mat1 17 - - [3] i; pu i/o pio1_1 ? general purpose digital input/output pin. -o ct32b1_mat1 ? match output 1 for 32-bit timer 1. pio1_2/ct32b1_mat2 34 - - [3] i; pu i/o pio1_2 ? general purpose digital input/output pin. -o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_3/ct32b1_mat3 50 - - [3] i; pu i/o pio1_3 ? general purpose digital input/output pin. -o ct32b1_mat3 ? match output 3 for 32-bit timer 1. pio1_4/ct32b1_cap0 16 - - [3] i; pu i/o pio1_4 ? general purpose digital input/output pin. -i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. pio1_5/ct32b1_cap1 32 - - [3] i; pu i/o pio1_5 ? general purpose digital input/output pin. -i ct32b1_cap1 ? capture input 1 for 32-bit timer 1. pio1_7 6 - - [3] i; pu i/o pio1_7 ? general purpose digital input/output pin. pio1_8 39 - - [3] i; pu i/o pio1_8 ? general purpose digital input/output pin. pio1_10 12 - - [3] i; pu i/o pio1_10 ? general purpose digital input/output pin. pio1_11 43 - - [3] i; pu i/o pio1_11 ? general purpose digital input/output pin. table 3. pin description (lpc1315/16/17 - no usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 15 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller pio1_13/dtr / ct16b0_mat0/txd 47 36 - [3] i; pu i/o pio1_13 ? general purpose digital input/output pin. -o dtr ? data terminal ready output for usart. -o ct16b0_mat0 ? match output 0 for 16-bit timer 0. -o txd ? transmitter output for usart. pio1_14/dsr / ct16b0_mat1/rxd 49 37 - [3] i; pu i/o pio1_14 ? general purpose digital input/output pin. -i dsr ? data set ready input for usart. -o ct16b0_mat1 ? match output 1 for 16-bit timer 0. -i rxd ? receiver input for usart. pio1_15/dcd / ct16b0_mat2/sck1 57 43 28 [3] i; pu i/o pio1_15 ? general purpose digital input/output pin. -i dcd ? data carrier detect input for usart. -o ct16b0_mat2 ? match output 2 for 16-bit timer 0. -i/o sck1 ? serial clock for ssp1. pio1_16/ri /ct16b0_cap0 63 48 - [3] i; pu i/o pio1_16 ? general purpose digital input/output pin. -i ri ? ring indicator input for usart. -i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio1_17/ct16b0_cap1/ rxd 23 - - [3] i; pu i/o pio1_17 ? general purpose digital input/output pin. -i ct16b0_cap1 ? capture input 1 for 16-bit timer 0. -i rxd ? receiver input for usart. pio1_18/ct16b1_cap1/ txd 28 - - [3] i; pu i/o pio1_18 ? general purpose digital input/output pin. -i ct16b1_cap1 ? capture input 1 for 16-bit timer 1. -o txd ? transmitter output for usart. pio1_19/dtr /ssel1 3 2 1 [3] i; pu i/o pio1_19 ? general purpose digital input/output pin. -o dtr ? data terminal ready output for usart. -i/o ssel1 ? slave select for ssp1. pio1_20/dsr /sck1 18 13 - [3] i; pu i/o pio1_20 ? general purpose digital input/output pin. -i dsr ? data set ready input for usart. -i/o sck1 ? serial clock for ssp1. pio1_21/dcd /miso1 35 26 - [3] i; pu i/o pio1_21 ? general purpose digital input/output pin. -i dcd ? data carrier detect input for usart. -i/o miso1 ? master in slave out for ssp1. pio1_22/ri /mosi1 51 38 - [3] i; pu i/o pio1_22 ? general purpose digital input/output pin. -i ri ? ring indicator input for usart. -i/o mosi1 ? master out slave in for ssp1. pio1_23/ct16b1_mat1/ ssel1 24 18 13 [3] i; pu i/o pio1_23 ? general purpose digital input/output pin. -o ct16b1_mat1 ? match output 1 for 16-bit timer 1. -i/o ssel1 ? slave select for ssp1. pio1_24/ct32b0_mat0 27 21 14 [3] i; pu i/o pio1_24 ? general purpose digital input/output pin. -o ct32b0_mat0 ? match output 0 for 32-bit timer 0. table 3. pin description (lpc1315/16/17 - no usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 16 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller pio1_25/ct32b0_mat1 2 1 - [3] i; pu i/o pio1_25 ? general purpose digital input/output pin. -o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_26/ct32b0_mat2/ rxd 14 11 - [3] i; pu i/o pio1_26 ? general purpose digital input/output pin. -o ct32b0_mat2 ? match output 2 for 32-bit timer 0. -i rxd ? receiver input for usart. pio1_27/ct32b0_mat3/ txd 15 12 - [3] i; pu i/o pio1_27 ? general purpose digital input/output pin. -o ct32b0_mat3 ? match output 3 for 32-bit timer 0. -o txd ? transmitter output for usart. pio1_28/ct32b0_cap0/ sclk 31 24 - [3] i; pu i/o pio1_28 ? general purpose digital input/output pin. -i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. -i/o sclk ? serial clock input/output for usart in synchronous mode. pio1_29/sck0/ ct32b0_cap1 41 31 - [3] i; pu i/o pio1_29 ? general purpose digital input/output pin. -i/o sck0 ? serial clock for ssp0. -i ct32b0_cap1 ? capture input 1 for 32-bit timer 0. pio1_31 - 25 - [3] i; pu i/o pio1_31 ? general purpose digital input/output pin. n.c. 25 19 - - - not connected. n.c. 26 20 - - - not connected. xtalin 8 6 4 [8] - - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 9 7 5 [8] - - output from the o scillator amplifier. v dda 59 - - - - analog 3.3 v pad supply voltage: this should be nominally the same voltage as v dd but should be isolated to minimize noise and error. this voltage is used to power the adc. this pin should be ti ed to 3.3 v if the adc is not used. vrefn 48 - - - - adc negative reference voltage: this should be nominally the same voltage as v ss but should be isolated to minimize noise and error. level on this pin is used as a reference for adc. table 3. pin description (lpc1315/16/17 - no usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 17 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled; ia = inactive, no pull-up/dow n enabled; f = floating; floating pins, if not used, should be ti ed to ground or power to minimize power consumption. [2] see figure 33 for the reset pad configuration. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an extern al pull-up resistor is required on this pin for the deep power-d own mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 32 ). [4] i 2 c-bus pins compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with configurable pull-up/pull-down resistors and configurable hysteresis ( see figure 32 ); includes high-current output driver. [6] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 32 ); includes programmable digital input glitch filter. [7] wakeup pin. 5 v tolerant pad providing digital i/o functions with configurable pull-up/pull-down resistors, configurable hys teresis, and analog input. when configured as a adc inpu t, digital section of the pad is disabl ed and the pin is not 5 v tolerant (see figure 32 ); includes digital input glitch filter. [8] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibilit y to noise). xtalout should be left floating. vrefp 64 - - - - adc positive reference voltage: this should be nominally the same voltage as v dda but should be isolated to minimize noise and error. level on this pin is used as a reference for adc. this pin should be tied to 3.3 v if the adc is not used. v ssa 55 - - - - analog ground: 0 v reference. this should nominally be the same voltage as v ss product data sheet but should be isolated to minimize noise and error. v dd 10; 33; 58 8; 44 6; 29 - - supply voltage to the internal regulator and the external rail. on lqfp48 and hvqfn33 packages, this pin is also connected to the 3.3 v adc supply and reference voltage. v ss 7; 54 5; 41 33 - - ground. table 3. pin description (lpc1315/16/17 - no usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 18 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller table 4. pin description (lpc1345/46/47 - with usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description reset /pio0_0 4 3 2 [2] i; pu i reset ? external reset input with 20 ns glitch filter. a low-going pulse as short as 50 ns on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. this pin also serves as the debug select input. low level selects the jtag boundary scan. high level selects the arm swd debug mode. -i/o pio0_0 ? general purpose digital input/output pin. pio0_1/clkout/ ct32b0_mat2/ usb_ftoggle 543 [3] i; pu i/o pio0_1 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler or the usb device enumeration. -o clkout ? clockout pin. -o ct32b0_mat2 ? match output 2 for 32-bit timer 0. -o usb_ftoggle ? usb 1 ms start-of-frame signal. pio0_2/ssel0/ ct16b0_cap0 13 10 8 [3] i; pu i/o pio0_2 ? general purpose digital input/output pin. i/o ssel0 ? slave select for ssp0. i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio0_3/usb_vbus 19 14 9 [3] i; pu i/o pio0_3 ? general purpose digital input/output pin. a low level on this pin during reset starts the isp command handler. a high level during reset starts the usb device enumeration. -i usb_vbus ? monitors the presence of usb bus power. pio0_4/scl 20 15 10 [4] ia i/o pio0_4 ? general purpose digital input/output pin (open-drain). -i/o scl ? i 2 c-bus clock input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_5/sda 21 16 11 [4] ia i/o pio0_5 ? general purpose digital input/output pin (open-drain). -i/o sda ? i 2 c-bus data input/output (open-drain). high-current sink only if i 2 c fast-mode plus is selected in the i/o configuration register. pio0_6/usb_connect / sck0 29 22 15 [3] i; pu i/o pio0_6 ? general purpose digital input/output pin. -o usb_connect ? signal used to switch an external 1.5 k ? resistor under software control. used with the softconnect usb feature. -i/o sck0 ? serial clock for ssp0. pio0_7/cts 30 23 16 [5] i; pu i/o pio0_7 ? general purpose digital input/output pin (high-current output driver). -i cts ? clear to send input for usart. pio0_8/miso0/ ct16b0_mat0 36 27 17 [3] i; pu i/o pio0_8 ? general purpose digital input/output pin. -i/o miso0 ? master in slave out for ssp0. -o ct16b0_mat0 ? match output 0 for 16-bit timer 0.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 19 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller pio0_9/mosi0/ ct16b0_mat1/ swo 37 28 18 [3] i; pu i/o pio0_9 ? general purpose digital input/output pin. -i/o mosi0 ? master out slave in for ssp0. -o ct16b0_mat1 ? match output 1 for 16-bit timer 0. -o swo ? serial wire trace output. swclk/pio0_10/sck0/ ct16b0_mat2 38 29 19 [3] i; pu i swclk ? serial wire clock and test clock tck for jtag interface. -i/o pio0_10 ? general purpose digital input/output pin. -o sck0 ? serial clock for ssp0. -o ct16b0_mat2 ? match output 2 for 16-bit timer 0. tdi/pio0_11/ad0/ ct32b0_mat3 42 32 21 [6] i; pu i tdi ? test data in for jtag interface. -i/o pio0_11 ? general purpose digital input/output pin. -i ad0 ? a/d converter, input 0. -o ct32b0_mat3 ? match output 3 for 32-bit timer 0. tms/pio0_12/ad1/ ct32b1_cap0 44 33 22 [6] i; pu i tms ? test mode select for jtag interface. -i/o pio_12 ? general purpose digital input/output pin. -i ad1 ? a/d converter, input 1. -i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. tdo/pio0_13/ad2/ ct32b1_mat0 45 34 23 [6] i; pu o tdo ? test data out for jtag interface. -i/o pio0_13 ? general purpose digital input/output pin. -i ad2 ? a/d converter, input 2. -o ct32b1_mat0 ? match output 0 for 32-bit timer 1. trst /pio0_14/ad3/ ct32b1_mat1 46 35 24 [6] i; pu i trst ? test reset for jtag interface. -i/o pio0_14 ? general purpose digital input/output pin. -i ad3 ? a/d converter, input 3. -o ct32b1_mat1 ? match output 1 for 32-bit timer 1. swdio/pio0_15/ad4/ ct32b1_mat2 52 39 25 [6] i; pu i/o swdio ? serial wire debug input/output. -i/o pio0_15 ? general purpose digital input/output pin. -i ad4 ? a/d converter, input 4. -o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio0_16/ad5/ ct32b1_mat3/wakeup 53 40 26 [7] i; pu i/o pio0_16 ? general purpose digital input/output pin. -i ad5 ? a/d converter, input 5. -o ct32b1_mat3 ? match output 3 for 32-bit timer 1. -i wakeup ? deep power-down mode wake-up pin with 20 ns glitch filter. this pin must be pulled high externally to enter deep power-down mode and pulled low to exit deep power-down mode. a low-going pulse as short as 50 ns wakes up the part. table 4. pin description (lpc1345/46/47 - with usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 20 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller pio0_17/rts / ct32b0_cap0/sclk 60 45 30 [3] i; pu i/o pio0_17 ? general purpose digital input/output pin. -o rts ? request to send output for usart. -i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. -i/o sclk ? serial clock input/output for usart in synchronous mode. pio0_18/rxd/ ct32b0_mat0 61 46 31 [3] i; pu i/o pio0_18 ? general purpose digital input/output pin. -i rxd ? receiver input for usart. used in uart isp mode. -o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio0_19/txd/ ct32b0_mat1 62 47 32 [3] i; pu i/o pio0_19 ? general purpose digital input/output pin. -o txd ? transmitter output for usart. used in uart isp mode. -o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio0_20/ct16b1_cap0 11 9 7 [3] i; pu i/o pio0_20 ? general purpose digital input/output pin. -i ct16b1_cap0 ? capture input 0 for 16-bit timer 1. pio0_21/ct16b1_mat0/ mosi1 22 17 12 [3] i; pu i/o pio0_21 ? general purpose digital input/output pin. -o ct16b1_mat0 ? match output 0 for 16-bit timer 1. -i/o mosi1 ? master out slave in for ssp1. pio0_22/ad6/ ct16b1_mat1/miso1 40 30 20 [6] i; pu i/o pio0_22 ? general purpose digital input/output pin. -i ad6 ? a/d converter, input 6. -o ct16b1_mat1 ? match output 1 for 16-bit timer 1. -i/o miso1 ? master in slave out for ssp1. pio0_23/ad7 56 42 27 [6] i; pu i/o pio0_23 ? general purpose digital input/output pin. -i ad7 ? a/d converter, input 7. pio1_0/ct32b1_mat0 1 - - [3] i; pu i/o pio1_0 ? general purpose digital input/output pin. -o ct32b1_mat0 ? match output 0 for 32-bit timer 1. pio1_1/ct32b1_mat1 17 - - [3] i; pu i/o pio1_1 ? general purpose digital input/output pin. -o ct32b1_mat1 ? match output 1 for 32-bit timer 1. pio1_2/ct32b1_mat2 34 - - [3] i; pu i/o pio1_2 ? general purpose digital input/output pin. -o ct32b1_mat2 ? match output 2 for 32-bit timer 1. pio1_3/ct32b1_mat3 50 - - [3] i; pu i/o pio1_3 ? general purpose digital input/output pin. -o ct32b1_mat3 ? match output 3 for 32-bit timer 1. pio1_4/ct32b1_cap0 16 - - [3] i; pu i/o pio1_4 ? general purpose digital input/output pin. -i ct32b1_cap0 ? capture input 0 for 32-bit timer 1. pio1_5/ct32b1_cap1 32 - - [3] i; pu i/o pio1_5 ? general purpose digital input/output pin. -i ct32b1_cap1 ? capture input 1 for 32-bit timer 1. pio1_7 6 - - [3] i; pu i/o pio1_7 ? general purpose digital input/output pin. pio1_8 39 - - [3] i; pu i/o pio1_8 ? general purpose digital input/output pin. table 4. pin description (lpc1345/46/47 - with usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 21 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller pio1_10 12 - - [3] i; pu i/o pio1_10 ? general purpose digital input/output pin. pio1_11 43 - - [3] i; pu i/o pio1_11 ? general purpose digital input/output pin. pio1_13/dtr / ct16b0_mat0/txd 47 36 - [3] i; pu i/o pio1_13 ? general purpose digital input/output pin. -o dtr ? data terminal ready output for usart. -o ct16b0_mat0 ? match output 0 for 16-bit timer 0. -o txd ? transmitter output for usart. pio1_14/dsr / ct16b0_mat1/rxd 49 37 - [3] i; pu i/o pio1_14 ? general purpose digital input/output pin. -i dsr ? data set ready input for usart. -o ct16b0_mat1 ? match output 1 for 16-bit timer 0. -i rxd ? receiver input for usart. pio1_15/dcd / ct16b0_mat2/sck1 57 43 28 [3] i; pu i/o pio1_15 ? general purpose digital input/output pin. -i dcd ? data carrier detect input for usart. -o ct16b0_mat2 ? match output 2 for 16-bit timer 0. -i/o sck1 ? serial clock for ssp1. pio1_16/ri /ct16b0_cap0 63 48 - [3] i; pu i/o pio1_16 ? general purpose digital input/output pin. -i ri ? ring indicator input for usart. -i ct16b0_cap0 ? capture input 0 for 16-bit timer 0. pio1_17/ct16b0_cap1/ rxd 23 - - [3] i; pu i/o pio1_17 ? general purpose digital input/output pin. -i ct16b0_cap1 ? capture input 1 for 16-bit timer 0. -i rxd ? receiver input for usart. pio1_18/ct16b1_cap1/ txd 28 - - [3] i; pu i/o pio1_18 ? general purpose digital input/output pin. -i ct16b1_cap1 ? capture input 1 for 16-bit timer 1. -o txd ? transmitter output for usart. pio1_19/dtr /ssel1 3 2 1 [3] i; pu i/o pio1_19 ? general purpose digital input/output pin. -o dtr ? data terminal ready output for usart. -i/o ssel1 ? slave select for ssp1. pio1_20/dsr /sck1 18 13 - [3] i; pu i/o pio1_20 ? general purpose digital input/output pin. -i dsr ? data set ready input for usart. -i/o sck1 ? serial clock for ssp1. pio1_21/dcd /miso1 35 26 - [3] i; pu i/o pio1_21 ? general purpose digital input/output pin. -i dcd ? data carrier detect input for usart. -i/o miso1 ? master in slave out for ssp1. pio1_22/ri /mosi1 51 38 - [3] i; pu i/o pio1_22 ? general purpose digital input/output pin. -i ri ? ring indicator input for usart. -i/o mosi1 ? master out slave in for ssp1. pio1_23/ct16b1_mat1/ ssel1 24 18 - [3] i; pu i/o pio1_23 ? general purpose digital input/output pin. -o ct16b1_mat1 ? match output 1 for 16-bit timer 1. -i/o ssel1 ? slave select for ssp1. table 4. pin description (lpc1345/46/47 - with usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 22 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller pio1_24/ct32b0_mat0 27 21 - [3] i; pu i/o pio1_24 ? general purpose digital input/output pin. -o ct32b0_mat0 ? match output 0 for 32-bit timer 0. pio1_25/ct32b0_mat1 2 1 - [3] i; pu i/o pio1_25 ? general purpose digital input/output pin. -o ct32b0_mat1 ? match output 1 for 32-bit timer 0. pio1_26/ct32b0_mat2/ rxd 14 11 - [3] i; pu i/o pio1_26 ? general purpose digital input/output pin. -o ct32b0_mat2 ? match output 2 for 32-bit timer 0. -i rxd ? receiver input for usart. pio1_27/ct32b0_mat3/ txd 15 12 - [3] i; pu i/o pio1_27 ? general purpose digital input/output pin. -o ct32b0_mat3 ? match output 3 for 32-bit timer 0. -o txd ? transmitter output for usart. pio1_28/ct32b0_cap0/ sclk 31 24 - [3] i; pu i/o pio1_28 ? general purpose digital input/output pin. -i ct32b0_cap0 ? capture input 0 for 32-bit timer 0. -i/o sclk ? serial clock input/output for usart in synchronous mode. pio1_29/sck0/ ct32b0_cap1 41 31 - [3] i; pu i/o pio1_29 ? general purpose digital input/output pin. -i/o sck0 ? serial clock for ssp0. -i ct32b0_cap1 ? capture input 1 for 32-bit timer 0. pio1_31 - 25 - [3] i; pu i/o pio1_31 ? general purpose digital input/output pin. usb_dm 25 19 13 [8] f- usb_dm ? usb bidirectional d ? line. (lpc1345/46/46 only.) usb_dp 26 20 14 [8] f- usb_dp ? usb bidirectional d+ line. (lpc1345/46/46 only.) xtalin 8 6 4 [9] - - input to the oscillator circuit and internal clock generator circuits. input voltage must not exceed 1.8 v. xtalout 9 7 5 [9] - - output from the o scillator amplifier. v dda 59 - - - - analog 3.3 v pad supply voltage: this should be nominally the same voltage as v dd but should be isolated to minimize noise and error. this voltage is used to power the adc. this pin should be tied to 3.3 v if the adc are not used. vrefn 48 - - - - adc negative reference voltage: this should be nominally the same voltage as v ss but should be isolated to minimize noise and error. level on this pin is used as a reference for adc. table 4. pin description (lpc1345/46/47 - with usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 23 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller [1] pin state at reset for default function: i = input; o = output; pu = internal pull-up enabled; ia = inactive, no pull-up/dow n enabled; f = floating; floating pins, if not used, should be ti ed to ground or power to minimize power consumption. [2] see figure 33 for the reset pad configuration. reset functionality is not available in deep power-down mode. use the wakeup pin to reset the chip and wake up from deep power-down mode. an extern al pull-up resistor is required on this pin for the deep power-d own mode. [3] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s and configurable hysteresis ( see figure 32 ). [4] i 2 c-bus pins compliant with the i 2 c-bus specification for i 2 c standard mode, i 2 c fast-mode, and i 2 c fast-mode plus. [5] 5 v tolerant pad providing digital i/o functions with configurable pull-up/pull-down resistors and configurable hysteresis ( see figure 32 ); includes high-current output driver. [6] 5 v tolerant pad providing digital i/o functions with conf igurable pull-up/pull-down resistor s, configurable hysteresis, and analog input. when configured as a adc input, digital section of the pad is disabled and the pin is not 5 v tolerant (see figure 32 ); includes programmable digital input glitch filter. [7] wakeup pin. 5 v tolerant pad providing digital i/o functions with configurable pull-up/pull-down resistors, configurable hys teresis, and analog input. when configured as a adc inpu t, digital section of the pad is disabl ed and the pin is not 5 v tolerant (see figure 32 ); includes digital input glitch filter. [8] pad provides usb functions. it is designed in accordance with the usb specification, revision 2.0 (full-speed and low-speed mode only). this pad is not 5 v tolerant. [9] when the system oscillator is not used, connect xtalin and xtalout as follows: xtalin can be left floating or can be grounde d (grounding is preferred to reduce susceptibility to noise). xtalout should be left floating.15 vrefp 64 - - - - adc positive reference voltage: this should be nominally the same voltage as v dda but should be isolated to minimize noise and error. level on this pin is used as a reference for adc. this pin should be tied to 3.3 v if the adc is not used. v ssa 55 - - - - analog ground: 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v dd 10; 33; 58 8; 44 6; 29 - - supply voltage to the internal regulator and the external rail. on lqfp48 and hvqfn33 packages, this pin is also connected to the 3.3 v adc supply and reference voltage. v ss 7; 54 5; 41 33 - - ground. table 4. pin description (lpc1345/46/47 - with usb) symbol LQFP64 lqfp48 hvqfn33 reset state [1] type description
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 24 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 7. functional description 7.1 on-chip flash programming memory the lpc1315/16/17/45/46/47 contain up to 64 kb on-chip flash program memory. the flash can be programmed using in-system programming (isp) or in-application programming (iap) via the on-chip boot loader software. flash updates via usb are supported as well. the flash memory is divided into 4 kb sector s with each sector consisting of 16 pages. individual pages of 256 byte each can be erased using the iap erase page command. 7.2 eeprom the lpc1315/16/17/45/46/47 contain 2 kb or 4 kb of on-chip byte-erasable and byte-programmable eeprom data memory . the eeprom can be programmed using in-application programming (iap) via the on-chip boot loader software. 7.3 sram the lpc1315/16/17/45/46/47 contain a total of 8 kb, 10 kb, or 12 kb on-chip static ram memory. 7.4 on-chip rom the on-chip rom contains the boot loader and the following application programming interfaces (apis): ? in-system programming (isp) and in-application programming (iap) support for flash including iap erase page command. ? iap support for eeprom ? usb api (hid, cdc, and msc drivers) (lpc1345/46/47 only) ? power profiles for configuring po wer consumption and pll settings ? flash updates via usb suppo rted (lpc1345/46/47 only) 7.5 memory map the lpc1315/16/17/45/46/47 inco rporates several distinct me mory regions, shown in the following figures. figure 8 shows the overall map of the entire address space from the user program viewpoint following reset. the interrupt vector area supports address remapping. the ahb peripheral area is 2 mb in size and is divided to allow for up to 128 peripherals. the apb peripheral area is 512 kb in size and is divided to allow fo r up to 32 peripherals. each peripheral of either type is allocated 16 kb of space. this allows simplifying the address decoding for each peripheral.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 25 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 7.6 nested vectored inte rrupt controller (nvic) the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m3. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. 7.6.1 features ? controls system exceptions and peripheral interrupts. ? in the lpc1315/16/17/45/46/47, the nvic supports up to 32 vectored interrupts. ? eight programmable interrupt priority leve ls with hardware pr iority level masking. fig 8. lpc1315/16/17/45/46/47 memory map apb peripherals 0x4000 4000 0x4000 8000 0x4000 c000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4003 8000 0x4003 c000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 c000 0x4004 c000 0x4005 8000 0x4005 c000 0x4006 0000 0x4006 4000 0x4006 8000 0x4008 0000 0x4002 4000 0x4001 c000 0x4001 4000 0x4000 0000 wwdt 32-bit counter/timer 0 32-bit counter/timer 1 adc usart/smart card pmu i 2 c-bus 20 - 21 reserved 10 - 13 reserved reserved reserved 26 - 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved 0x0000 0000 0 gb 0.5 gb 4 gb 1 gb 0x1000 2000 0x1fff 0000 0x1fff 4000 0x2000 0000 0x5000 0000 0x5000 4000 0xffff ffff reserved reserved reserved 2 kb usb sram (lpc134x) reserved 0x4000 0000 0x4008 0000 0x4008 4000 apb peripherals usb gpio 0x2000 4000 0x2000 4800 2 kb sram1 (lpc1317/47) 0x2000 0800 8 kb sram0 0x1000 0000 lpc1315/16/17/45/46/47 0x0000 c000 0x0000 8000 48 kb on-chip flash (lpc1316/46) 0x0001 0000 64 kb on-chip flash (lpc1317/47) 32 kb on-chip flash (lpc1315/45) 16 kb boot rom 0x0000 0000 0x0000 00c0 active interrupt vectors 002aag562 reserved reserved ssp0 ssp1 16-bit counter/timer 1 16-bit counter/timer 0 iocon system control 19 gpio pin interrupt 22 23 gpio group0 interrupt 24 gpio group1 interrupt 25 ri timer flash/eeprom controller 0xe000 0000 0xe010 0000 private peripheral bus
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 26 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller ? software interr upt generation. 7.6.2 interrupt sources each peripheral device has one interrupt line connected to the nvic but may have several interrupt flags. individual interrupt flags may also represent more than one interrupt source. 7.7 iocon block the iocon block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. activi ty of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7.1 features ? programmable pull-up, pull-down, or repeater mode. ? all gpio pins (except pio0_4 and pio0_5) are pulled up to 3.3 v (v dd = 3.3 v) if their pull-up resistor is enabled. ? programmable pseudo open-drain mode. ? programmable 10-ns glitch filter on pi ns pio0_22, pio0_23, and pio0_11 to pio0_16. the glitch filter is turned off by default. ? programmable hysteresis. ? programmable input inverter. 7.8 general purpose input/output gpio device pins that are not connec ted to a specific peripheral function are controlled by the gpio registers. pins may be dynamically configured as inputs or outputs. multiple outputs can be set or cleared in one write operation. lpc1315/16/17/45/46/47 use accelerated gpio functions: ? gpio registers are a dedicated ahb peripheral so that the fastest possible i/o timing can be achieved. ? entire port value can be written in one instruction. any gpio pin providing a digital function can be programmed to generate an interrupt on a level, a rising or falling edge, or both. the gpio block consists of three parts: 1. the gpio ports. 2. the gpio pin interrupt block to control eight gpio pins selected as pin interrupts. 3. two gpio group interrupt blocks to control two combined interrupts from all gpio pins.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 27 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 7.8.1 features ? gpio pins can be configured as input or output by software. ? all gpio pins default to inputs with interrupt disabled at reset. ? pin registers allow pins to be sensed and set individually. ? up to eight gpio pins can be selected from all gpio pins to create an edge- or level-sensitive gpio interrupt request. ? port interrupts can be triggered by any pin or pins in each port. 7.9 usb interface remark: the usb interface is available on parts lpc1345/46/47 only. the universal serial bu s (usb) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. the host controller allocates the usb bandwidth to attached devices through a token-based protocol. the bus supports hot-plugging and dynamic configuration of the de vices. all transactions are initiated by the host controller. the lpc1345/46/47 usb interfac e consists of a full-speed dev ice controller with on-chip phy (physical layer) for device functions. remark: configure the lpc1345/46/47 in def ault power mode with the power profiles before using the usb (see section 7.18.5.1 ). do not use the usb with the part in performance, efficiency, or low-power mode. 7.9.1 full-speed usb device controller the device controller enables 12 mbit/s data exchange with a usb host controller. it consists of a register interface, serial interface engine, and endpoint buffer memory. the serial interface engine decodes the usb data stream and writes data to the appropriate endpoint buffer. the status of a completed usb transfer or error condition is indicated via status registers. an interrupt is also generated if enabled. 7.9.1.1 features ? dedicated usb pll available. ? fully compliant with usb 2.0 specification (full speed) . ? supports 10 physical (5 logical) endpoints including one control endpoint. ? single and double buffering supported. ? each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. ? supports wake-up from deep-sleep mode and power-down mode on usb activity and remote wake-up. ? supports softconnect. ? supports link power management (lpm). 7.10 usart the lpc1315/16/17/45/46/47 contains one usart.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 28 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller the usart includes full modem control, su pport for synchronous mode, and a smart card interface. the rs-485/9-bit mode a llows both software address detection and automatic address detection using 9-bit mode. the usart uses a fractional baud rate generator. standard baud rates such as 115200 bd can be achieved with any crystal frequency above 2 mhz. 7.10.1 features ? maximum usart data bit rate of 3.125 mbit/s. ? 16-byte receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? fractional divider for baud rate control, auto baud capabilities and fifo control mechanism that enables software flow control implementation. ? support for rs-485/9-bit mode. ? support for modem control. ? support for synchronous mode. ? includes smart card interface (iso 7816-3). 7.11 ssp serial i/o controller the ssp controllers are capable of operation on a ssp, 4-wire ssi, or microwire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given da ta transfer. the ssp supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. in practice, often only one of these data flows carries meaningful data. 7.11.1 features ? maximum ssp speed of 25 mbit/s (master) or 4.17 mbit/s (slave) (in ssp mode) ? compatible with motorola spi, 4-wire texas instruments ssi, and national semiconductor microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? 4-bit to 16-bit frame 7.12 i 2 c-bus serial i/o controller the lpc1315/16/17/45/46/47 contain one i 2 c-bus controller. the i 2 c-bus is bidirectional for inter-ic contro l using only two wires: a serial clock line (scl) and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an lcd driver) or a transmitter with the capability to both receive and send information (such as me mory). transmitters and/or
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 29 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c is a multi-master bus and can be controlled by more than one bus master connected to it. 7.12.1 features ? the i 2 c-interface is an i 2 c-bus compliant interface with open-drain pins. the i 2 c-bus interface supports fast-mode plus with bit rates up to 1 mbit/s. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus can be used for test and diagnostic purposes. ? the i 2 c-bus controller supports multiple address recognition and a bus monitor mode. 7.13 12-bit adc the lpc1315/16/17/45/46/47 contains one adc. it is a single 12-bit successive approximation adc with eight channels. 7.13.1 features ? 12-bit successive approximation adc. ? input multiplexing among 8 pins and three internal sources. ? low-power mode. ? 10-bit double-conversion rate mode (conversion rate of up to 1 msample/s). ? measurement range vrefn to vrefp (typically 3 v; not to exceed vdda voltage level). ? 12-bit conversion rate of up to 500 khz. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition of input pin or timer match signal. ? on the LQFP64 package, power and reference pins (v dda , v ssa , vrefp, vrefn) are brought out on separate pins for superior noise immunity. 7.14 general purpose externa l event counter/timers the lpc1315/16/17/45/46/47 includes tw o 32-bit counter/timers and two 16-bit counter/timers. the counter/time r is designed to count cycles of the system derived clock. it can optionally generate interrupts or perf orm other actions at specified timer values, based on four match registers. each counter/ti mer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 30 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 7.14.1 features ? a 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler. ? counter or timer operation. ? one capture channel per timer, that can ta ke a snapshot of the timer value when an input signal transitions. a capture event may also generate an interrupt. ? four match registers per timer that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? up to four external outputs corresponding to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. ? the timer and prescaler may be configured to be cleared on a designated capture event. this feature permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capt uring the timer value on the trailing edge. 7.15 repetitive inte rrupt (ri) timer the repetitive interrupt timer provides a free-r unning 48-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. any bits of the timer/compare can be masked such that they do not contribute to the match detection. the repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 7.15.1 features ? 48-bit counter running from the main cloc k. counter can be free-running or can be reset when an rit interrupt is generated. ? 48-bit compare value. ? 48-bit compare mask. an interrupt is generated when the counter value equals the compare value, after masking. this allows for co mbinations not poss ible with a simple compare. ? support for etm timestamp generator. 7.16 system tick timer the arm cortex-m3 includes a system tick timer (systic k) that is inte nded to generate a dedicated systick exception at a fi xed time interval (typically 10 ms). 7.17 windowed watc hdog timer (wwdt) the purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 31 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 7.17.1 features ? internally resets chip if not periodically reloaded during the programmable time-out period. ? optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. ? optional warning interrupt can be generated at a programmable time prior to watchdog time-out. ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect feed sequence causes reset or interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 24-bit timer with internal prescaler. ? selectable time period from (t cy(wdclk) ? 256 ? 4) to (t cy(wdclk) ? 2 24 ? 4) in multiples of t cy(wdclk) ? 4. ? the watchdog clock (wdclk) source can be selected from the irc or the watchdog oscillator (wdo). this gives a wide range of potential timing choices of watchdog operation under different power conditions. 7.18 clocking and power control 7.18.1 integrated oscillators the lpc1315/16/1 7/45/46/47 include th ree independent oscilla tors. these are the system oscillator, the internal rc oscillato r (irc), and the watchdog oscillator. each oscillator can be used for more than one purpo se as required in a pa rticular application. following reset, the lpc1315/16 /17/45/46/47 will opera te from the internal rc oscillator until switched by software. this allows system s to operate without any external crystal and the bootloader code to oper ate at a known frequency. see figure 9 for an overview of the lpc1315 /16/17/45/46/47 clock generation.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 32 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 7.18.1.1 internal rc oscillator the irc may be used as the clock source for th e wdt, and/or as the clock that drives the system pll and subsequently the cpu. the nominal irc frequency is 12 mhz. the irc is trimmed to 1 % accuracy over the entire voltage and temperature range. the usb clock divider is avai lable on parts lpc1345/46/47 only. fig 9. lpc1315/16/17/45/46/47 cloc king generation block diagram system oscillator watchdog oscillator irc oscillator usb pll usbpllclksel (usb clock select) system clock divider sysahbclkctrln (ahb clock enable) cpu, system control, pmu memories, peripheral clocks ssp0 peripheral clock divider ssp0 ssp1 peripheral clock divider ssp1 usart peripheral clock divider uart wdt wdclksel (wdt clock select) clkoutsel (clkout clock select) usb 48 mhz clock divider usb watchdog oscillator irc oscillator system oscillator usbclksel (usb clock select) clkout pin clock divider clkout pin 002aag563 system clock system pll irc oscillator system oscillator watchdog oscillator mainclksel (main clock select) syspllclksel (system pll clock select) main clock irc oscillator n
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 33 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller upon power-up, any chip reset, or wake-up from deep power-down mode, the lpc1315/16/17/45/46/47 use the irc as the cl ock source. software may later switch to one of the other available clock sources. 7.18.1.2 system oscillator the system oscillator can be used as the clock source for the cpu, with or without using the pll. on the lpc1315/16/ 17/45/46/47, the system oscillato r must be used to provide the clock source to usb. the system oscillator operates at frequencies of 1 mhz to 25 mhz. this frequency can be boosted to a higher frequency, up to the maximum cpu operating frequency, by the system pll. 7.18.1.3 watchdog oscillator the watchdog oscillator can be used as a clock source that directly drives the cpu, the watchdog timer, or the clkout pin. the watchdog oscillator nominal frequency is programmable between 9.4 khz and 2.3 mhz. th e frequency spread over processing and temperature is ? 40 % (see also ta b l e 1 3 ). 7.18.2 system pll and usb pll the lpc1315/16/17/45/46/47 contain a sys tem pll and a dedicated pll for generating the 48 mhz usb clock. the system and usb plls are identical. the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up to a high frequency with a curren t controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is provid ing the desired output frequency. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. the pll output frequency must be lower than 100 mhz. since th e minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, and then connect to the pll as a clock source. the pll settling time is 100 ? s. 7.18.3 clock output the lpc1315/16/17/45/46/47 features a clo ck output function that routes the irc oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.18.4 wake-up process the lpc1315/16/17/45/46/47 begin operation at power-up and when awakened from deep power-down mode by us ing the 12 mhz irc oscillator as the clock source. this allows chip operation to resume quickly. if th e main oscillator or the pll is needed by the application, software will need to enable these features an d wait for them to stabilize before they are used as a clock source. 7.18.5 power control the lpc1315/16/17/45/46/47 support a variety of power control features. there are four special modes of processor power reduction: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. the cpu clock rate may also be
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 34 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller controlled as needed by changing clock sources, reconfiguring pll values, and/or altering the cpu clock divider value. this allows a trade-off of power versus processing speed based on application requirements. in addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. selected peripherals have their ow n clock divider which provides even better power control. 7.18.5.1 power profiles the power consumption in active and sleep modes can be optimized for the application through simple calls to the power profile. the power configuration routine configures the lpc1315/16/17/45/46/47 for one of the following power modes: ? default mode corresponding to power configuration after reset. ? cpu performance mode co rresponding to optimize d processing capability. ? efficiency mode corresponding to optimize d balance of current consumption and cpu performance. ? low-current mode corresponding to lowest power consumption. in addition, the power profile includes routines to select the optimal pll settings for a given system clock and pll input clock. remark: when using the usb, configure the lpc1345/46/47 in default mode. 7.18.5.2 sleep mode when sleep mode is entered, the clock to the core is stopped. resumption from the sleep mode does not need any special sequence but re-enabling the clock to the arm core. in sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.18.5.3 deep-sleep mode in deep-sleep mode, the lpc1315/16/17/45/4 6/47 is in sleep-mode and all peripheral clocks and all clock sources are off with the exception of the irc. the irc output is disabled unless the irc is selected as input to the watchdog timer. in addition all analog blocks are shut down and the flash is in st and-by mode. in deep-sleep mode, the user has the option to keep the watc hdog oscillator and the bod circuit running for self-timed wake-up and bod protection. the lpc1315/16/17/45/46/47 can wake up from deep-sleep mode via reset, selected gpio pins, a watchdog timer interrupt, or an interrupt generating usb port activity. deep-sleep mode saves power and allows for short wake-up times.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 35 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 7.18.5.4 power-down mode in power-down mode, the lpc1315/16/17/45/4 6/47 is in sleep-mode and all peripheral clocks and all clock sources ar e off with the exception of watc hdog oscillator if selected. in addition all analog blocks and the flash are shut down. in power-down mode, the user has the option to keep the bod circuit running for bod protection. the lpc1315/16/17/45/46/47 can wake up fr om power-down mode via reset, selected gpio pins, a watchdog timer interrupt, or an interrupt generating usb port activity. power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times. 7.18.5.5 deep power-down mode in deep power-down mode, power is shut off to the entire chip with the exception of the wakeup pin. the lpc1315/16/ 17/45/46/47 can wake up fr om deep powe r-down mode via the wakeup pin. the lpc1315/16/17/45/46/47 can be prevented from entering deep power-down mode by setting a lock bit in the pmu block. locking out deep power-down mode enables the user to always keep the watchdog timer or the bod running. when entering deep power-down mode, an external pull-up resistor is required on the wakeup pin to hold it high. the reset pin must also be held high to prevent it from floating while in deep power-down mode. 7.18.6 system control 7.18.6.1 reset reset has four sources on the lp c1315/16/17/45/4 6/47: the reset pin, the watchdog reset, power-on reset (por), and the brownout detection (bod) circuit. the reset pin is a schmitt trigger input pin. assertion of chip reset by any source, once the operating voltage attains a usable level, starts th e irc and initializes the flash controller. a low-going pulse as short as 50 ns resets the part. when the internal reset is removed, the proc essor begins executing at address 0, which is initially the reset vector mapped from the bo ot block. at that point, all of the processor and peripheral registers have been in itialized to predetermined values. an external pull-up resistor is required on the reset pin if deep power-down mode is used. 7.18.6.2 brownout detection the lpc1315/16/17/45/46/47 includes up to four levels for monitoring the voltage on the v dd pin. if this voltage falls below one of selected levels, the bod asserts an interrupt signal to the nvic. this signal can be enabled for interrupt in the interrupt enable register in the nvic in order to cause a cpu interrupt; if not, software can monitor the signal by reading a dedicated status register . four threshold levels can be selected to cause a forced reset of the chip.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 36 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 7.18.6.3 code security (code read protection - crp) this feature of the lpc1315/16/17/45/46/47 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the serial wire debugger (swd) and in-system programming (isp) can be restricted. when needed, crp is invoked by programming a specific pattern into a dedicated flash location. iap commands are not affected by the crp. in addition, isp entry via the pio0_1 pin can be disabled without enabling crp. for details see the lpc1315/16/17/45/46/47 user manual . there are three levels of code read protection: 1. crp1 disables access to the chip via the swd and allows partial flash update (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash fi eld updates are needed but all sectors can not be erased. 2. crp2 disables access to the chip via the swd and only allows full flash erase and update using a reduced set of the isp commands. 3. running an application with level crp3 select ed fully disables any access to the chip via the swd pins and the isp. this mode effectively disables isp override using pio0_1 pin, too. it is up to the user?s application to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via the usart. in addition to the three crp levels, sampli ng of pin pio0_1 for valid user code can be disabled. for details see the lpc1315/16/17/45/46/47 user manual . 7.18.6.4 apb interface the apb peripherals are located on one apb bus. 7.18.6.5 ahblite the ahblite connects the cpu bus of the arm cortex-m3 to the flash memory, the main static ram, and the rom. 7.18.6.6 external interrupt inputs all gpio pins can be level or edge sensitive interrupt inputs. 7.19 emulation and debugging debug functions are integrated into the arm co rtex-m3. serial wire debug functions are supported in addition to a standard jt ag boundary scan. the arm cortex-m0 is configured to support up to four breakpoints and two watch points. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 37 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller the reset pin selects between the jtag boundary scan (reset = low) and the arm swd debug (reset = high). the arm swd debug port is disabled while the lpc1315/16/17/45/46/47 is in reset. remark: boundary scan operations should not be started until 250 ? s after por, and the test tap should be reset after the boundary scan. boundary scan is not affected by code read protection. remark: the jtag interface cannot be used for debug purposes.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 38 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] including voltage on outputs in 3-state mode. [3] the maximum non-operating storage temperature is different t han the temperature for required shelf life which should be dete rmined based on required shelf lifetime. please refer to t he jedec spec (j-std-033b.1) for further details. [4] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd supply voltage (core and external rail) 2.0 3.6 v v i input voltage 5 v tolerant i/o pins; only valid when the v dd supply voltage is present [2] ? 0.5 +5.5 v i dd supply current per supply pin - 100 ma i ss ground current per ground pin - 100 ma i latch i/o latch-up current ? (0.5v dd ) < v i < (1.5v dd ); t j < 125 ?c -100ma t stg storage temperat ure non-operating [3] ? 65 +150 ?c t j(max) maximum junction temperature - 150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5w v esd electrostatic discharge voltage human body model; all pins [4] ? 5000 +5000 v
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 39 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 9. static characteristics table 6. static characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd supply voltage (core and external rail) [2] 2.0 3.3 3.6 v i dd supply current active mode; v dd =3.3v; t amb =25 ? c; code while(1){} executed from flash; system clock = 1 mhz [3] [5] [6] [7] [8] [9] -0.5-ma system clock = 12 mhz [4] [5] [6] [7] [8] [9] -2-ma system clock = 72 mhz [5] [6] [7] [8] [9] [10] -14-ma sleep mode; v dd = 3.3 v; t amb =25 ?c; system clock = 12 mhz [4] [5] [6] [7] [8] [9] -1-ma deep-sleep mode; v dd = 3.3 v; t amb =25 ?c [5] [8] - 280 - ? a power-down mode; v dd =3.3v; t amb =25 ?c [5] [8] -2.1- ? a deep power-down mode; v dd =3.3v; t amb =25 ?c [11] - 220 - na standard port pins, reset i il low-level input current v i = 0 v; on-chip pull-up resistor disabled -0.510na i ih high-level input current v i =v dd ; on-chip pull-down resistor disabled -0.510na i oz off-state output current v o =0v; v o =v dd ; on-chip pull-up/down resistors disabled -0.510na v i input voltage pin configured to provide a digital function [12] [13] [14] 0- 5.0v v o output voltage output active 0 - v dd v v ih high-level input voltage 0.7v dd --v v il low-level input voltage - - 0.3v dd v v hys hysteresis voltage - 0.4 - v v oh high-level output voltage 2.5 v ? v dd ? 3.6 v; i oh = ? 4 ma v dd ? 0.4 - - v 2.0 v ? v dd ??? 2.5 v; i oh = ? 3 ma v dd ? 0.4 - - v v ol low-level output voltage 2.5 v ? v dd ? 3.6 v; i ol =4 ma - - 0.4 v 2.0 v ? v dd ??? 2.5 v; i ol =3 ma - - 0.4 v
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 40 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller i oh high-level output current 2.5 v ? v dd ? 3.6 v; v oh =v dd ? 0.4 v ? 4- - ma 2.0 v ? v dd ??? 2.5 v; v oh =v dd ? 0.4 v ? 3- - ma i ol low-level output current 2.5 v ? v dd ? 3.6 v; v ol =0.4v 4 - - ma 2.0 v ? v dd ??? 2.5 v; v ol =0.4v 3 - - ma i ohs high-level short-circuit output current v oh =0v [15] -- ? 45 ma i ols low-level short-circuit output current v ol =v dd [15] --50ma i pd pull-down current v i = 5 v 10 50 150 ? a i pu pull-up current v i =0v; 2.0 v ?? v dd ? 3.6 v ? 15 ? 50 ? 85 ? a v dd = 2.0 v ? 10 ? 50 ? 85 ? a v dd lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 41 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] for usb operation 3.0 v ? v dd ? 3.6 v. guaranteed by design. i pu pull-up current v i =0v 2.0 v < v dd ? 3.6 v ? 15 ? 50 ? 85 ? a v dd = 2.0 v ? 10 ? 50 ? 85 ? a v dd lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 42 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller [3] system oscillator enabled; pll and irc disabled. [4] irc enabled; system oscillator disabled; system pll disabled. [5] i dd measurements were performed with all pins configured as gpio outputs driven low and pull-up resistors disabled. [6] bod disabled. [7] all peripherals disabled in the ahbclkctrl register. peri pheral clocks to usart, ssp0/1 disabled in the syscon block. [8] usb_dp and usb_dm pulled low externally. [9] low-current mode pwr_low_current selected when runni ng the set_power routine in the power profiles. [10] irc disabled; system oscill ator enabled; system pll enabled. [11] wakeup pin pulled high externally. an exte rnal pull-up resistor is required on the reset pin for the deep power-down mode. [12] including voltage on outputs in 3-state mode. [13] v dd supply voltage must be present. [14] 3-state outputs go into 3-state mode in deep power-down mode. [15] allowed as long as the current limit does not exceed the maximum current allowed by the device. [16] to v ss . [17] includes external resistors of 33 ?? 1 % on usb_dp and usb_dm. 9.1 bod static characteristics [1] interrupt levels are selected by writing the le vel value to the bod control register bodctrl, see lpc1315/16/17/45/46/47 user manual . table 7. bod static characteristics [1] t amb =25 ? c. symbol parameter conditions min typ max unit v th threshold voltage interrupt level 1 assertion - 2.22 - v de-assertion - 2.35 - v interrupt level 2 assertion - 2.52 - v de-assertion - 2.66 - v interrupt level 3 assertion - 2.80 - v de-assertion - 2.90 - v reset level 0 assertion - 1.46 - v de-assertion - 1.63 - v reset level 1 assertion - 2.06 - v de-assertion - 2.15 - v reset level 2 assertion - 2.35 - v de-assertion - 2.43 - v reset level 3 assertion - 2.63 - v de-assertion - 2.71 - v
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 43 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 9.2 power consumption power measurements in active, sleep, and deep-sleep modes were performed under the following conditions (see lpc1315/16/17/45/46/47 user manual ): ? configure all pins as gpio with pull-up resistor disabled in the iocon block. ? configure gpio pins as outputs using the gpiondir registers. ? write 0 to all gpiondata registers to drive the outputs low. conditions: t amb = 25 ? c; active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; bod disabled; all peripher als disabled in the sysahbclkctrl register; all peripheral clocks disabled; usb_dp and usb_dm pulled low externally. 1 mhz - 6 mhz: system oscillator enabled; pll, irc disabled. 12 mhz: irc enabled; system oscillator, pll disabled. 24 mhz - 72 mhz: irc disabled; system oscillator, pll enabled. fig 10. typical supply current versus regulator supply voltage v dd in active mode 002aag900 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 0 6 12 18 v dd (v) i dd (ma) 72 mhz 60 mhz 48 mhz 36 mhz 24 mhz 12 mhz 6 mhz 3 mhz 1 mhz
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 44 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; active mode entered executing code while(1){} from flash; internal pull-up resistors disabled; bo d disabled; all peripherals di sabled in the sysahbclkctrl register; all peripheral clo cks disabled; usb_dp and usb_ dm pulled low externally. 1 mhz - 6 mhz: system oscillator enabled; pll, irc disabled. 12 mhz: irc enabled; system oscillator, pll disabled. 24 mhz - 72 mhz: irc disabled; system oscillator, pll enabled. fig 11. typical supply current versus temperature in active mode conditions: v dd = 3.3 v; sleep mode entered from flash; internal pull-up resistors disabled; bod disabled; all peripherals disabled in the sysahbclkc trl register; all peripher al clocks disabled; usb_dp and usb_dm pulled low externally. 1 mhz - 6 mhz: system oscillator enabled; pll, irc disabled. 12 mhz: irc enabled; system oscillator, pll disabled. 24 mhz - 72 mhz: irc disabled; system oscillator, pll enabled. fig 12. typical supply current ver sus temperature in sleep mode 002aag901 -40 -15 10 35 60 85 0 3.6 7.2 10.8 14.4 18 temperature (c) i dd (ma) 72 mhz 60 mhz 48 mhz 36 mhz 24 mhz 12 mhz 6 mhz 3 mhz 1 mhz 002aag902 -40 -15 10 35 60 85 0 2 4 6 temperature (c) i dd (ma) 72 mhz 60 mhz 48 mhz 36 mhz 24 mhz 12 mhz 6 mhz 3 mhz 1 mhz
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 45 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller conditions: bod disabled; all oscillators and analog blocks turned off in the pdsleepcfg register; usb_dp and usb_dm pulled low externally. fig 13. typical supply current versus temperature in deep-sleep mode conditions: bod disabled; all oscillators and analog blocks turned off in the pdsleepcfg register; usb_dp and usb_dm pulled low externally. fig 14. typical supply current versus temperature in power-down mode 002aag891 -40 -15 10 35 60 85 250 260 270 280 290 300 temperature (c) i dd (a) 3.6 v 3.3 v 2.0 v 002aag892 -40 -15 10 35 60 85 0 6 12 18 temperature (c) i dd (a) 3.6 v 3.3 v 2.0 v
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 46 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 15. typical supply current versus temperature in deep power-down mode 002aag893 -40 -15 10 35 60 85 0 0.2 0.4 0.6 0.8 temperature (c) i dd (a) 3.6 v 3.3 v 2.0 v table 8. power consumption for individual analog and digital blocks the supply current per peripheral is meas ured as the difference in supply current between the peripheral block enabled and the peripheral block disa bled in the sysahbclkctrl or pdruncfg (for ana log blocks) registers. all other blocks are disabled in both registers and no code is ex ecuted. measured on a typical sample at t amb =25 ? c. unless noted otherwise, the system oscillator and pll are running in both measurements. typical supply current per peripheral in ma for different system clock frequencies notes n/a 12 mhz 48 mhz 72 mhz irc 0.23 - - - system oscillator running; pll off; independent of main clock frequency. system oscillator at 12 mhz 0.23 - - - irc running; pll off; independent of main clock frequency. watchdog oscillator at 500 khz/2 0.002 - - - system oscillator running; pll off; independent of main clock frequency. bod 0.045 - - - independent of main clock frequency. main pll or usb pll - 0.260.340.48 adc - 0.07 0.25 0.37 clkout - 0.14 0.56 0.82 main clock divided by 4 in the clkoutdiv register. ct16b0 - 0.010.050.08 ct16b1 - 0.010.040.06 ct32b0 - 0.010.050.07 ct32b1 - 0.010.040.06 gpio - 0.21 0.80 1.17 gpio pins configured as outputs and set to low. direction and pin state are maintained if the gpio is disabled in the sysahbclkcfg register. iocon - 0.00 0.02 0.02 i2c - 0.03 0.12 0.17
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 47 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 9.3 electrical pi n characteristics rom - 0.04 0.15 0.22 ssp0 - 0.11 0.41 0.60 ssp1 - 0.11 0.41 0.60 usart - 0.20 0.76 1.11 wdt - 0.01 0.05 0.08 main clock select ed as clock source for the wdt. usb - - 1.2 - table 8. power consumption for individual analog and digital blocks the supply current per peripheral is meas ured as the difference in supply current between the peripheral block enabled and the peripheral block disa bled in the sysahbclkctrl or pdruncfg (for ana log blocks) registers. all other blocks are disabled in both registers and no code is ex ecuted. measured on a typical sample at t amb =25 ? c. unless noted otherwise, the system oscillator and pll are running in both measurements. typical supply current per peripheral in ma for different system clock frequencies notes n/a 12 mhz 48 mhz 72 mhz conditions: v dd = 3.3 v; on pin pio0_7. fig 16. high-drive output: typical high-level output voltage v oh versus high-level output current i oh . i oh (ma) 0 60 40 20 10 50 30 002aae990 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 48 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; on pins pio0_4 and pio0_5. fig 17. i 2 c-bus pins (high current sink): typical low-level output current i ol versus low-level output voltage v ol conditions: v dd = 3.3 v; standard port pins and pio0_7. fig 18. typical low-l evel output current i ol versus low-level output voltage v ol v ol (v) 0 0.6 0.4 0.2 002aaf019 20 40 60 i ol (ma) 0 t = 85 c 25 c ?40 c v ol (v) 0 0.6 0.4 0.2 002aae991 5 10 15 i ol (ma) 0 t = 85 c 25 c ?40 c
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 49 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 19. typical high-level output voltage v oh versus high-level output source current i oh conditions: v dd = 3.3 v; standard port pins. fig 20. typical pull-up current i pu versus input voltage v i i oh (ma) 0 24 16 8 002aae992 2.8 2.4 3.2 3.6 v oh (v) 2 t = 85 c 25 c ?40 c v i (v) 0 5 4 23 1 002aae988 ?30 ?50 ?10 10 i pu (a) ?70 t = 85 c 25 c ?40 c
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 50 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller conditions: v dd = 3.3 v; standard port pins. fig 21. typical pull-down current i pd versus input voltage v i v i (v) 0 5 4 23 1 002aae989 40 20 60 80 i pd (a) 0 t = 85 c 25 c ?40 c
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 51 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 10. dynamic characteristics 10.1 flash/eeprom memory [1] number of program/erase cycles. [2] programming times are given for writing 256 bytes from ram to the flash. data must be written to the flash in blocks of 256 bytes. 10.2 external clock [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. table 9. flash characteristics t amb = ? 40 ? c to +85 ? c, unless otherwise specified. symbol parameter conditions min typ max unit n endu endurance [1] 10000 100000 - cycles t ret retention time powered 10 - - years unpowered 20 - - years t er erase time sector or multiple consecutive sectors 95 100 105 ms t prog programming time [2] 0.95 1 1.05 ms table 10. eeprom characteristics t amb = ? 40 ? cto+85 ? c; v dd = 2.7 v to 3.6 v. symbol parameter conditions min typ max unit f clk clock frequency 200 375 400 khz n endu endurance 100000 1000000 - cycles t ret retention time powered 100 200 - years unpowered 150 300 - years t er erase time 64 bytes - 1.8 - ms t prog programming time 64 bytes - 1.1 - ms table 11. dynamic characteristic: external clock t amb = ? 40 ? c to +85 ? c; v dd over specified ranges. [1] symbol parameter conditions min typ [2] max unit f osc oscillator frequency 1 - 25 mhz t cy(clk) clock cycle time 40 - 1000 ns t chcx clock high time t cy(clk) ? 0.4 - - ns t clcx clock low time t cy(clk) ? 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 52 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 22. external clock timing (with an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 53 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 10.3 internal oscillators [1] parameters are valid over operating temp erature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [1] typical ratings are not guaranteed. the va lues listed are at nom inal supply voltages. [2] the typical frequency spread over processing and temperature (t amb = ?40 ? c to +85 ? c) is ? 40 %. [3] see the lpc1315/16/17/45/46/47 user manual. table 12. dynamic char acteristics: irc t amb = ? 40 ? c to +85 ? c; 2.7 v ? v dd ? 3.6 v [1] . symbol parameter conditions min typ [2] max unit f osc(rc) internal rc oscillator frequency - 11.88 12 12.12 mhz conditions: frequency values are typical values. 12 mhz ? 1 % accuracy is guaranteed for 2.7 v ? v dd ? 3.6 v and t amb = ?40 ? c to +85 ? c. variations between parts may cause the irc to fall outside the 12 mhz ? 1 % accuracy specification for voltages below 2.7 v. fig 23. internal rc oscillator frequency versus temperature table 13. dynamic characterist ics: watchdog oscillator symbol parameter conditions min typ [1] max unit f osc(int) internal oscillator frequency divsel = 0x1f, freqsel = 0x1 in the wdtoscctrl register; [2] [3] -9.4-khz divsel = 0x00, freqsel = 0xf in the wdtoscctrl register [2] [3] - 2300 - khz 002aaf403 11.95 12.05 12.15 f (mhz) 11.85 temperature ( c) ?40 85 35 10 60 ?15 vdd = 3.6 v 3.3 v 3.0 v 2.7 v 2.4 v 2.0 v
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 54 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 10.4 i/o pins [1] applies to standard port pins and reset pin. 10.5 i 2 c-bus [1] see the i 2 c-bus specification um10204 for details. [2] parameters are valid over operating tem perature range unless otherwise specified. [3] thd;dat is the data hold time that is measured from the fa lling edge of scl; applies to data in transmission and the acknowl edge. [4] a device must internally provide a hold time of at least 300 ns for the sda signal (with respect to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is s pecified at 300 ns. the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection re sistors to be connected in between the sda and the scl pins and the sda/scl bus lines without exceeding the maximum specified t f . [7] in fast-mode plus, fall time is specified the same for bot h output stage and bus timing. if se ries resistors are used, desig ners should allow for this when c onsidering bus timing. table 14. dynamic characteristics: i/o pins [1] t amb = ? 40 ? c to +85 ? c; 3.0 v ? v dd ? 3.6 v. symbol parameter conditions min typ max unit t r rise time pin configured as output 3.0 - 5.0 ns t f fall time pin configured as output 2.5 - 5.0 ns table 15. dynamic characteristic: i 2 c-bus pins [1] t amb = ? 40 ? c to +85 ? c. [2] symbol parameter conditions min max unit f scl scl clock frequency standard-mode 0 100 khz fast-mode 0 400 khz fast-mode plus 0 1 mhz t f fall time [4] [5] [6] [7] of both sda and scl signals standard-mode -3 0 0n s fast-mode 20 + 0.1 ? c b 300 ns fast-mode plus - 120 ns t low low period of the scl clock standard-mode 4.7 - ? s fast-mode 1.3 - ? s fast-mode plus 0.5 - ? s t high high period of the scl clock standard-mode 4.0 - ? s fast-mode 0.6 - ? s fast-mode plus 0.26 - ? s t hd;dat data hold time [3] [4] [8] standard-mode 0 - ? s fast-mode 0 - ? s fast-mode plus 0 - ? s t su;dat data set-up time [9] [10] standard-mode 250 - ns fast-mode 100 - ns fast-mode plus 50 - ns
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 55 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller [8] the maximum t hd;dat could be 3.45 ? s and 0.9 ? s for standard-mode and fast-mode but must be less than the maximum of t vd;dat or t vd;ack by a transition time (see um10204 ). this maximum must only be met if th e device does not stretch the low period (t low ) of the scl signal. if the clock stretches the scl, the data must be valid by the set-up time before it releases the clock. [9] tsu;dat is the data set-up time that is measured with respec t to the rising edge of scl; applies to data in transmission and the acknowledge. [10] a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system but the requirement t su;dat = 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stre tch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. al so the acknowledge timing must meet this set-up time. fig 24. i 2 c-bus pins clock timing 002aaf425 t f 70 % 30 % sda t f 70 % 30 % s 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 70 % 30 % 70 % 30 % t vd;dat t high t low t su;dat
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 56 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 10.6 ssp interface [1] t cy(clk) = (sspclkdiv ? (1 + scr) ? cpsdvsr) / f main . the clock cycle time deriv ed from the spi bit rate t cy(clk) is a function of the main clock frequency f main , the ssp peripheral clock divider (sspclkdiv), the ssp scr parameter (specified in the ssp0cr0 register), and the ssp cpsdvsr parameter (spec ified in the ssp clock prescale register). [2] t amb = ?40 ? c to 85 ? c. [3] t cy(clk) = 12 ? t cy(pclk) . [4] t amb = 25 ? c; v dd = 3.3 v. table 16. dynamic characteristics: ssp pins in spi mode symbol parameter conditions min max unit ssp master t cy(clk) clock cycle time full-duplex mode [1] 40 - ns when only transmitting [1] 27.8 - ns t ds data set-up time in spi mode; 2.4 v ? v dd ? 3.6 v [2] 15 - ns 2.0 v ? v dd < 2.4 v [2] 20 - ns t dh data hold time in spi mode [2] 0- n s t v(q) data output valid time in spi mode [2] -1 0n s t h(q) data output hold time in spi mode [2] 0- n s ssp slave t cy(pclk) pclk cycle time 13.9 - ns t ds data set-up time in spi mode [3] [4] 0- n s t dh data hold time in spi mode [3] [4] 3 ? t cy(pclk) + 4 - ns t v(q) data output valid time in spi mode [3] [4] -3 ? t cy(pclk) + 11 ns t h(q) data output hold time in spi mode [3] [4] -2 ? t cy(pclk) + 5 ns
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 57 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 25. ssp master timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh data valid data valid t h(q) data valid data valid t v(q) cpha = 1 cpha = 0 002aae829
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 58 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 26. ssp slave timing in spi mode sck (cpol = 0) mosi miso t cy(clk) t clk(h) t clk(l) t ds t dh t v(q) data valid data valid t h(q) sck (cpol = 1) data valid data valid mosi miso t ds t dh t v(q) data valid data valid t h(q) data valid data valid cpha = 1 cpha = 0 002aae830
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 59 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 11. adc electrical characteristics [1] select the adc low-power mode by setting the lp wrmode bit in the adc cr register. see the lpc1315/16/17/45/46/47 user manual . [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 27 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 27 . [5] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 27 . [6] adcoffs value (bits 7:4) = 2 in the adc trm register. see the lpc1315/16/17/45/46/47 user manual . [7] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 27 . [8] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 27 . [9] see figure 27 . [10] the conversion frequency corresponds to the number of samples per second. table 17. adc characteristics v dda = 2.7 v to 3.6 v; t amb = ? 40 ? c to +85 ? c unless otherwise specifie d; 12-bit resolution. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance - 5 - pf i dda(adc) adc analog supply current on pin v dda (LQFP64 package only) low-power mode [1] -5- ? a during adc conversions -350- ? a e d differential linearity error [2] [3] --? 1lsb e l(adj) integral non-linearity [4] --? 5lsb e o offset error [5] [6] --? 2.5 lsb e g gain error [7] --? 0.3 % e t absolute error [8] --7l s b r vsi voltage source interface resistance [9] -1-k ? f clk(adc) adc clock frequency - - 15.5 mhz f c(adc) adc conversion frequency [10] --5 0 0k h z
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 60 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 27. 12-bit adc characteristics 002aad948 4095 4094 4093 4092 4091 (2) (1) 4096 4090 4091 4092 4093 4094 4095 7 123456 7 6 5 4 3 2 1 0 4090 (5) (4) (3) 1 lsb (ideal) code out vrefp ? vrefn 4096 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 61 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 12. application information 12.1 suggested usb interface solutions 12.2 xtal input the input voltage to the on-chip oscillators is limited to 1.8 v. if the oscillator is driven by a clock in slave mode, it is recommended that th e input be coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, choose an additional capacitor to ground c g which attenuates the input voltage by a factor c i /(c i + c g ). in slave mode, a minimum of 200 mv(rms) is needed. fig 28. usb interface on a self-powered device lpc1345/46/47 usb-b connector usb_dp usb_connect soft-connect switch usb_dm usb_vbus v ss v dd r1 1.5 k r s = 33 002aag564 r s = 33 fig 29. usb interface on a bus-powered device lpc1345/46/47 v dd r1 1.5 k 002aag565 usb-b connector usb_dp usb_dm usb_vbus v ss r s = 33 r s = 33
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 62 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller in slave mode the input clock signal should be coupled by means of a capacitor of 100 pf ( figure 30 ), with an amplitude between 200 mv(rms) and 1000 mv(rms). this corresponds to a square wave signal with a signal swing of between 280 mv and 1.4 v. the xtalout pin in this configur ation can be left unconnected. external components and models used in oscillation mode are shown in figure 31 and in ta b l e 1 8 and ta b l e 1 9 . since the feedback resistance is integrated on chip, only a crystal and the capacitances c x1 and c x2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequenc y is represen ted by l, c l and r s ). capacitance c p in figure 31 represents the parallel package capacitance and should not be larger than 7 pf. parameters f osc , c l , r s and c p are supplied by the crystal manufacturer. fig 30. slave mode operation of the on-chip oscillator fig 31. oscillator modes and models: oscillation mode of operation and external crystal model used for c x1 /c x2 evaluation table 18. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 1 mhz - 5 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 300 ? 39 pf, 39 pf 30 pf < 300 ? 57 pf, 57 pf lpc1xxx xtalin c i 100 pf c g 002aae788 002aaf424 lpc1xxx xtalin xtalout c x2 c x1 xtal = c l c p r s l
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 63 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 12.3 xtal printed-circuit boar d (pcb) layout guidelines the crystal should be connected on the pcb as close as poss ible to the oscillator input and output pins of the chip. take care that the load capacitors c x1 , c x2 , and c x3 in case of third overtone crystal usage have a common ground plane. the external components must also be connected to the ground plain. loops must be made as small as possible in order to keep the noise coupled in via the pcb as small as possible. also parasitics should stay as small as possible. values of c x1 and c x2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. 5 mhz - 10 mhz 10 pf < 300 ? 18 pf, 18 pf 20 pf < 200 ? 39 pf, 39 pf 30 pf < 100 ? 57 pf, 57 pf 10 mhz - 15 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 60 ? 39 pf, 39 pf 15 mhz - 20 mhz 10 pf < 80 ? 18 pf, 18 pf table 19. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) high frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2 15 mhz - 20 mhz 10 pf < 180 ? 18 pf, 18 pf 20 pf < 100 ? 39 pf, 39 pf 20 mhz - 25 mhz 10 pf < 160 ? 18 pf, 18 pf 20 pf < 80 ? 39 pf, 39 pf table 18. recommended values for c x1 /c x2 in oscillation mode (crystal and external components parameters) low frequency mode fundamental oscillation frequency f osc crystal load capacitance c l maximum crystal series resistance r s external load capacitors c x1 , c x2
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 64 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 12.4 standard i/o pad configuration figure 32 shows the possible pin modes for standard i/o pins with analog input function: ? digital output driver ? digital input: pull-up enabled/disabled ? digital input: pull-down enabled/disabled ? digital input: repeater mode enabled/disabled ? analog input fig 32. standard i/o pad configuration pin v dd v dd esd v ss esd strong pull-up strong pull-down v dd weak pull-up weak pull-down open-drain enable output enable repeater mode enable pull-up enable pull-down enable select data inverter data output data input select glitch filter analog input select analog input 002aaf695 pin configured as digital output driver pin configured as digital input pin configured as analog input 10 ns rc glitch filter
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 65 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 12.5 reset pad configuration 12.6 adc usage notes the following guidelines show how to increase the performance of the adc in a noisy environment beyond the adc specifications listed in ta b l e 1 7 : ? the adc input trace must be short and as close as possible to the lpc1315/16/17/45/46/47 chip. ? the adc input traces must be shielded from fast switching digital signals and noisy power supply lines. ? because the adc and the digital core share the same power supply, the power supply line must be adequately filtered. ? to improve the adc performance in a very no isy environment, put the device in sleep mode during the adc conversion. remark: on the LQFP64 package, the analog power supply and the reference voltage can be connected on separate pins for better noise immunity. fig 33. reset pad configuration v ss reset 002aaf274 v dd v dd v dd r pu esd esd 20 ns rc glitch filter pin
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 66 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 13. package outline fig 34. package outline hvqfn33 references outline version european projection issue date iec jedec jeita - - - hvqfn33_po 09-03-17 09-03-23 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 7.1 7.0 6.9 4.85 4.70 4.55 7.1 7.0 6.9 0.65 4.55 0.75 0.60 0.45 0.1 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33: plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 7 x 7 x 0.85 mm a 1 b 0.35 0.28 0.23 cd (1) d h e (1) e h 4.85 4.70 4.55 ee 1 e 2 4.55 lv 0.1 w 0.05 y 0.08 y 1 0 2.5 5 mm scale terminal 1 index area b a d e c y c y 1 x detail x a 1 a c b e 2 e 1 e e ac b v c w terminal 1 index area d h e h l 9 16 32 33 25 17 24 8 1
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 67 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 35. package outline lqfp48 (sot313-2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1)(1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 68 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 36. package outline LQFP64 (sot314-2) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1)(1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 69 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 14. soldering fig 37. reflow soldering of the hvqfn33 package footprint information for reflow soldering of hvqfn33 package 001aao134 occupied area solder land solder resist solder land plus solder paste solder paste deposit dimensions in mm remark: stencil thickness: 0.125 mm e = 0.65 evia = 4.25 owdtot = 5.10 oa pid = 7.25 pa+oa oid = 8.20 oa 0.20 sr chamfer (4) 0.45 dm evia = 1.05 w = 0.30 cu evia = 4.25 evia = 2.40 lbe = 5.80 cu lbd = 5.80 cu pie = 7.25 pa+oa lae = 7.95 cu lad = 7.95 cu oie = 8.20 oa owetot = 5.10 oa ehs = 4.85 cu dhs = 4.85 cu 4.55 sr 4.55 sr b-side (a-side fully covered) number of vias: 20 solder resist covered via 0.30 ph 0.60 sr cover 0.60 cu sehtot = 2.70 sp sdhtot = 2.70 sp gape = 0.70 sp spe = 1.00 sp 0.45 dm spd = 1.00 sp gapd = 0.70 sp
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 70 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 38. reflow soldering of the lqfp48 package sot313-2 dimensions in mm occupied area footprint information for reflow soldering of lqfp48 package ax bx gx gy hy hx ayby p1 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 10.350 p2 0.560 10.350 7.350 7.350 p1 0.500 0.280 c 1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout p2
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 71 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller fig 39. reflow soldering of the LQFP64 package sot314-2 dimensions in mm occupied area footprint information for reflow soldering of LQFP64 package ax bx gx gy hy hx ayby p1 p2 d2 (8) d1 (0.125) ax ay bx by d1 d2 gx gy hx hy 13.300 13.300 10.300 10.300 p1 0.500 p2 0.560 0.280 c 1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr solder land c generic footprint pattern refer to the package outline drawing for actual layout
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 72 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 15. abbreviations table 20. abbreviations acronym description a/d analog-to-digital adc analog-to-digital converter ahb advanced high-performance bus apb advanced peripheral bus bod brownout detection cdc communication device class etm embedded trace macrocell gpio general purpose input/output hid human interface device jtag joint test action group msc mass storage class pll phase-locked loop rc resistor-capacitor spi serial peripheral interface ssi serial synchronous interface ssp synchronous serial port tap test access port usart universal synchronous asynchronous receiver/transmitter
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 73 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 16. revision history table 21. revision history document id release date data sheet status change notice supersedes lpc1315_16_17_45_46_47 v.3 20120920 product data sheet - lpc1315_16_17_45_46_47 v.2 ? reflow soldering drawing corrected for the hvqfn33 package. see figure 37 . ? bod interrupt trigger level 0 removed. see table 7 . ? pin configuration diagrams updated: orientation of index sector relative to part marking corrected in figure 4 to figure 7 . lpc1315_16_17_45_46_47 v.2 20120718 product data sheet - lpc1315_16_17_45_46_47 v.1 modifications: ? data sheet status changed to product data sheet. ? parameters v ol , v oh , i ol , i oh updated for voltage range 2.0 v ? v dd < 2.5 v in table 6 . ? condition ?the peak current is limited to 25 times the corresponding maximum current.? removed from parameters i dd and i ss in ta b l e 5 . ? typical operating frequencies of the watchdog oscillator corrected in table 13 and section 7.18.1.3 . lpc1315_16_17_45_46_47 v.1 20120229 preliminary data sheet --
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 74 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. 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nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 75 of 77 nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
lpc1315_16_17_45_46_47 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights res erved. product data sheet rev. 3 ? 20 september 2012 76 of 77 continued >> nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . 12 7 functional description . . . . . . . . . . . . . . . . . . 24 7.1 on-chip flash programming memory . . . . . . . 24 7.2 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 on-chip rom . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.6 nested vectored interrupt controller (nvic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.6.2 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 26 7.7 iocon block . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 general purpose input/output gpio . . . . . . . 26 7.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.9 usb interface . . . . . . . . . . . . . . . . . . . . . . . . 27 7.9.1 full-speed usb device controller . . . . . . . . . . 27 7.9.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.10 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.11 ssp serial i/o controller . . . . . . . . . . . . . . . . . 28 7.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.12 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 28 7.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.13 12-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.14 general purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.15 repetitive interrupt (ri) timer . . . . . . . . . . . . . 30 7.15.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.16 system tick timer . . . . . . . . . . . . . . . . . . . . . . 30 7.17 windowed watchdog timer (wwdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.17.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.18 clocking and power control . . . . . . . . . . . . . . 31 7.18.1 integrated oscillators . . . . . . . . . . . . . . . . . . . 31 7.18.1.1 internal rc oscillator . . . . . . . . . . . . . . . . . . . 32 7.18.1.2 system oscillator . . . . . . . . . . . . . . . . . . . . . . 33 7.18.1.3 watchdog oscillator . . . . . . . . . . . . . . . . . . . . 33 7.18.2 system pll and usb pll. . . . . . . . . . . . . . . 33 7.18.3 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.18.4 wake-up process . . . . . . . . . . . . . . . . . . . . . . 33 7.18.5 power control . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.18.5.1 power profiles . . . . . . . . . . . . . . . . . . . . . . . . 34 7.18.5.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.18.5.3 deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 34 7.18.5.4 power-down mode . . . . . . . . . . . . . . . . . . . . . 35 7.18.5.5 deep power-down mode . . . . . . . . . . . . . . . . 35 7.18.6 system control . . . . . . . . . . . . . . . . . . . . . . . . 35 7.18.6.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.18.6.2 brownout detection . . . . . . . . . . . . . . . . . . . . 35 7.18.6.3 code security (code read protection - crp) . . . . . . . . . . . 36 7.18.6.4 apb interface . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.18.6.5 ahblite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.18.6.6 external interr upt inputs . . . . . . . . . . . . . . . . . 36 7.19 emulation and debugging . . . . . . . . . . . . . . . 36 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38 9 static characteristics . . . . . . . . . . . . . . . . . . . 39 9.1 bod static characteristics . . . . . . . . . . . . . . . 42 9.2 power consumption . . . . . . . . . . . . . . . . . . . 43 9.3 electrical pin characteristics. . . . . . . . . . . . . . 47 10 dynamic characteristics. . . . . . . . . . . . . . . . . 51 10.1 flash/eeprom memory . . . . . . . . . . . . . . . . 51 10.2 external clock. . . . . . . . . . . . . . . . . . . . . . . . . 51 10.3 internal oscillators . . . . . . . . . . . . . . . . . . . . . 53 10.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.5 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.6 ssp interface . . . . . . . . . . . . . . . . . . . . . . . . . 56 11 adc electrical characteristics . . . . . . . . . . . . 59 12 application information . . . . . . . . . . . . . . . . . 61 12.1 suggested usb interface solutions . . . . . . . . 61 12.2 xtal input . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.3 xtal printed-circuit board (pcb) layout guidelines . . . . . . . . . . . . . . . . . 63 12.4 standard i/o pad configuration . . . . . . . . . . . 64 12.5 reset pad configuration . . . . . . . . . . . . . . . . . 65 12.6 adc usage notes. . . . . . . . . . . . . . . . . . . . . . 65 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 66 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 72 16 revision history . . . . . . . . . . . . . . . . . . . . . . . 73 17 legal information . . . . . . . . . . . . . . . . . . . . . . 74 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 74
nxp semiconductors lpc1315/16/17/45/46/47 32-bit arm cortex-m3 microcontroller ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 20 september 2012 document identifier: lpc1315_16_17_45_46_47 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 75 18 contact information. . . . . . . . . . . . . . . . . . . . . 75 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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